Why is my VHDL counter not outputting pulses as desired?

Why is my VHDL counter not outputting pulses as desired?

I am working on creating a variable-frequency pulse train to control a
motor, and am using the following code to generate pulses using a counter
that counts up by some input increment value INC. I then pipe the MSB of
the output of my counter, DOUT[31], to an output pin on my FPGA. This
should give me a 50% duty cycle square wave of the desired frequency, but
I am getting nothing on the output pin. Is there something obviously wrong
with my code?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity VAR_COUNT is
port(
INC : in std_logic_vector(31 downto 0);
CLK : in std_logic;
CLEAR : in std_logic;
CLK_EN : in std_logic;
DOUT : out std_logic_vector(31 downto 0)
);
end VAR_COUNT;
architecture behavior of VAR_COUNT is
-- Define our count variable
signal COUNT:std_logic_vector(31 downto 0) := x"00_00_00_00";
-- Define our clock process
begin clk_proc:process(CLK)
begin
if CLEAR = '1' then -- clear the counter
COUNT <= COUNT - COUNT;
elsif CLK_EN = '1' then -- increment the counter
if (CLK'EVENT AND CLK = '1') then
COUNT <= COUNT + INC;
end if;
end if;
end process clk_proc;
-- concurrent assignment statement
DOUT <= COUNT;
end behavior;
The square wave frequency should be given by the equation pulse_freq =
clock_freq * INC / 2^32 for a 32-bit counter.
I am also trying to generate a single clock-cycle pulse by passing the MSB
of my counter output, DOUT[31](k) through a single-bit D-Q flip-flop to
get DOUT[31](k-1) and then executing:
pulse = ~DOUT[31](k) * DOUT[31](k-1)
where ~ represents logical NOT, and * represents logical AND. This should
give me a single clock-cycle pulse only when the counter rolls over.
Neither this nor the MSB itself (50% duty cycle square wave) are showing
when I read the output pin using an oscilloscope. Please let me know if
you see any errors in my code.
Thank you for your help!